1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and, more particularly, to a method of manufacturing an element isolation region of a semiconductor device formed on an SOI (Silicon On Insulator) substrate.
2. Description of the Prior Art
At present, high-breakdown-voltage devices used in power control devices have been available as semiconductor devices mounted on a semiconductor substrate having an SOI structure, i.e., on the SOI layer of an SOI substrate. Further, next-generation CMOS devices which operate at low voltages are fabricated on such an SOI substrate, and the practicability is variously examined.
Of the next-generation CMOS devices, a semiconductor device having a hyperfine CMOS transistor is formed on an SOI substrate having a very thin SOI layer (this semiconductor device will be referred to as an ultrathin SOI device hereinafter). In this case, the SOI layer serving as a channel layer is completely depleted to effectively suppress the short-channel effect.
As the element isolation technique of a semiconductor device mounted on this SOI substrate, LOCOS (Local Oxidation of Silicon) is mainly used, similar to a semiconductor device mounted on a normal bulk silicon substrate. Prior arts about the element isolation technique for the ultrathin SOI device include the one described in "Technical Digest", VLSI Symposium, 1993, pp. 25-26.
The prior art will be described with reference to FIGS. 1A to 1E. FIGS. 1A to 1E are sectional views, respectively, showing the steps in manufacturing an element isolation insulating film on a conventional SOI substrate.
As shown in FIG. 1A, a buried oxide layer 22 is formed on a silicon substrate 21, and an SOI layer 23 is formed on the buried oxide layer 22. The SOI substrate is a SIMOX (Separation by Implanted Oxygen) substrate. The SOI layer 23 is about 60 nm thick, and the buried oxide layer 22 is 400 nm thick.
A silicon oxide film 24 and a silicon nitride film mask 25 are formed and patterned on the SOI layer 23 by photolithography and dry etching. The silicon nitride film mask 25 is changed into an oxide mask, and the exposed SOI layer 23 is thermally oxidized. This thermal oxidization changes the exposed SOI layer 23 into an element isolation insulating film 26, as shown in FIG. 1B. The element isolation insulating film 26 is about 100 nm thick.
A silicon oxide film (not shown) formed on the silicon nitride film mask 25 by thermal oxidization is etched and removed in an aqueous hydrofluoric acid solution. The silicon nitride film mask 25 is etched and removed in an aqueous phosphoric acid solution at about 180.degree. C. The silicon oxide film mask 24 is etched in an aqueous hydrofluoric acid solution. In this manner, the surface of the SOI layer 23 is exposed, as shown in FIG. 1C. The surface of the element isolation insulating film 26 is also etched in etching the silicon oxide film mask 24 to become thin.
As shown in FIG. 1D, the surface of the SOI layer 23 is thermally oxidized to form a protective oxide film 27. Impurity ions are implanted through the protective oxide film 27. By this ion implantation, the impurity concentration in the SOI layer 23 is adjusted to form the channel region of a CMOS transistor.
As shown in FIG. 1E, the protective oxide film 27 on the SOI layer 23 is etched and removed in an aqueous hydrofluoric acid solution. In this etching step, the surface of the element isolation insulating film 26 is further etched to form a residual element isolation insulating film 26a. The residual element isolation insulating film 26a is very thin. Alternatively, the residual element isolation insulating film 26a may not exist, and the buried oxide layer 22 on the silicon substrate 21 may be etched.
In a subsequent step (not shown), the SOI substrate shown in FIG. 1E is thermally oxidized to form a gate oxide film on the surface of the SOI layer 23. A gate electrode is formed on this gate oxide film, and source and drain regions are further formed to form a CMOS transistor.
In the above-described prior art, the dielectric breakdown voltage of the gate oxide film of the CMOS transistor decreases, or the dielectric breakdown voltage varies on the SOI substrate.
As described in the prior art, this is because the thickness of the SOI layer of the ultrathin SOI device greatly decreases to decrease the original thickness of the element isolation insulating film 26. More specifically, if the thickness of the element isolation insulating film 26 decreases in this manner, the element isolation insulating film 26 is easily etched and removed in the process of manufacturing an ultrathin SOI device, as described above. Alternatively, a region where the element isolation insulating film is etched and removed is formed on the SOI substrate, and the buried oxide layer 22 is also partially etched in this region. The buried oxide layer 22 is recessed at the end portion of the SOI layer 23 to form a wedge-shaped end portion of the SOI layer. The dielectric breakdown voltage of the gate oxide film formed at this end portion of the SOI layer greatly decreases.